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UL631H256
Low Voltage SoftStore 32K x 8 nvSRAM
Features High-p erformance CMOS nonvolatile static RAM 32768 x 8 bits 35 and 45 ns Access Times 15 and 20 ns Output Enable Access Times Software STORE Initiation Automatic STORE Timing 106 STORE cycles to EEPROM 100 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation Unlimited RECALL cycles from EEPROM Unlimited Read and Write to SRAM Wide voltage range: 2.7 ... 3.6 V (3.0 ... 3.6 V for 35 ns type) Operating temperature range: 0 to 70 C -40 to 85 C QS 9000 Quality Standard RoHS compliance and Pb- free ESD protection > 2000 V (MIL STD 883C M3015.7-HBM) Package: SOP28 (330 mil) Description The UL631H256 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The UL631H256 is a fast static RAM (35 and 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through software sequences. The UL631H256 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. The UL631H256 is pin compatible with standard SRAMs.
Pin Configuration
Pin Description
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SOP
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
G A11 A9 A8 A13 W n. c. VCC n. c. A14 A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
n.c. A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 n.c.
Signal Name A0 - A14 DQ0 - DQ7 E G W VCC VSS
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground
Top View
Top View
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UL631H256
Block Diagram
A5 A6 A7 A8 A9 A11 A12 A13 A14 DQ0 DQ1 Input Buffers DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 EEPROM Array 512 x (64 x 8) STORE Row Decoder SRAM Array 512 Rows x 64 x 8 Columns
Store/ Recall Control
RECALL
VCC VSS
VCC
Column I/O Column Decoder
Software Detect
A0 - A13
A0 A1 A2 A3 A4 A10
G
E W
Truth Table for SRAM Operations Operating Mode Standby/not selected Internal Read Read Write * H or L Characteristics
All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten -times, in which cases transition is measured 200 mV from steady-state voltage.
E H L L L
W
*
G
*
DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
H H L
H L
*
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature C-Type K-Type
Symbol VCC VI VO PD Ta Tstg
Min. -0.5 -0.3 -0.3
Max. 4.6 VCC+0.5 VCC+0.5 1
Unit V V V W C C C
0 -40 -65
70 85 150
a: Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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UL631H256
Recommended Operating Conditions Power Supply Voltage Symbol VCC Conditions tc = 35 ns tc = 45 ns -2 V at Pulse Width 10 ns permitted Min. 3.0 2.7 -0.3 2.2 Max. 3.6 3.6 0.8 VCC+0.3 Unit V V V V
Input Low Voltage Input High Voltage
VIL VIH
C-Type DC Characteristics Operating Supply Currentb Symbol ICC1 VCC VIL VIH tc tc Average Supply Current during STORE c ICC2 VCC E W VIL VIH VCC W VIL VIH VCC E tc tc Standby Supply Curentd (Stable CMOS Input Levels) ICC(SB) VCC E VIL VIH Conditions Min. = 3.6 V = 0.8 V = 2.2 V = 35 ns = 45 ns = 3.6 V VCC -0.2 V VCC -0.2 V 0.2 V VCC -0.2 V = 3.6V VCC -0.2 V 0.2 V VCC -0.2 V = 3.6 V VIH = 35ns = 45 ns = 3.6 V VCC -0.2 V 0.2 V VCC -0.2 V 11 9 0.7 45 35 3 Max.
K-Type Unit Min. Max.
47 37 4
mA mA mA
Average Supply Current at tcR = 200 nsb (Cycling CMOS Input Levels) Standby Supply Currentd (Cycling TTL Input Levels)
ICC3
10
11
mA
ICC(SB)1
12 10 0.7
mA mA mA
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded The current ICC1 is measured for WRITE/READ - ratio of 1/2. c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE). d: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
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UL631H256
C-Type DC Characteristics Symbol VCC IOH IOL VCC VOH VOL VCC High Low Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ IIH IIL VIH VIL VCC E or G VOH VOL Conditions Min. Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current VOH VOL IOH IOL = VCCmin =-2 mA = 2 mA = VCCmin = 2.4 V = 0.4 V = 3.6 V = 3.6 V = 0V = 3.6 V V IH = 3.6 V = 0V 1 -1 -1 1 A A 2.4 0.4 -2 2 2 Max. Min. 2.4 0.4 -2 Max. V V mA mA K-Type Unit
1 -1 -1
1
A A
SRAM Memory Operations
No. 1 2 3 4 5 6 7 8 9
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time to Data Validg Chip Enable Access Time to Data Valid Output Enable Access Time to Data Valid E HIGH to Output in High-Zh G HIGH to Output in High-Zh E LOW to Output in Low-Z G LOW to Output in Low-Z Output Hold Time after Addr. Changeg
Symbol Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL IEC tcR ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) tPU tPD 5 0 3 0 Min. 35
35
45 Unit Max. 45 35 35 15 13 13 5 0 3 45 45 20 15 15 ns ns ns ns ns ns ns ns ns ns 35 45 ns
10 Chip Enable to Power Activee 11 Chip Disable to Power Standbyd, e
e: f: g: h:
Parameter guaranteed but not tested. Device is continuously selected with E and G both Low. Address valid prior to or coincident with E transition LOW. Measured 200 mV from steady state output voltage.
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UL631H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = V IH)f
tcR
(1)
Ai DQi
Output Previous Data Valid tv(A) (9)
Address Valid ta(A) (2) Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR (1)
Ai E G DQi
Output High Impedance tPU (10) ACTIVE STANDBY
Address Valid ta(A) (2) ta(E) (3) ten(E) (7) ta(G) (4) ten(G) (8)
tPD (11) tdis(E) (5) tdis(G) (6) Output Data Valid
ICC
No. Switching Characteristics Write Cycle 12 Write Cycle Time 13 Write Pulse Width 14 Write Pulse Width Setup Time 15 Address Setup Time 16 Address Valid to End of Write 17 Chip Enable Setup Time 18 Chip Enable to End of Write 19 Data Setup Time to End of Write 20 Data Hold Time after End of Write 21 Address Hold after End of Write 22 W LOW to Output in High-Zh, i 23 W HIGH to Output in Low-Z
Symbol Alt. #1 Alt. #2 IEC Min.
35
Max. Min.
45
Unit Max.
tAVAV tWLWH
tAVAV
tcW tw(W)
35 25 25 0 25 25 25 12 0 0 13 5
45 30 30 0 30 30 30 15 0 0 15 5
ns ns ns ns ns ns ns ns ns ns ns ns
tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVEH
tsu(W) tsu(A) tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W)
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UL631H256
Write Cycle #1: W-controlledj
tcW
(12)
Ai E W DQi
Input tsu(A)
(15)
Address Valid tsu(E) (17) tsu(A-WH) (16) tw(W) (13) tsu(D) (19) tdis(W) (12) Previous Data
th(A) (21)
th(D) (20)
Input Data Valid ten(W) (23) High Impedance
DQi
Output
Write Cycle #2: E-controlledj
tcW (12)
Ai E W DQi
Input tsu(A) (15)
Address Valid tw(E) (18) tsu(W) (14) tsu(D) (19) th(D) (20) th(A) (21)
Input Data Valid High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i: j:
If W is low and when E goes low, the outputs remain in the high impedance state. E or W must be > VIH during address transitions.
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UL631H256
Nonvolatile Memory Operations
No.
STORE Cycle Inhibit and Automatic Power Up RECALL
Symbol Min. Alt. tRESTORE VSWITCH 2.4 IEC 650 2.7 s V Max. Unit
24 Power Up RECALL Durationk Low Voltage Trigger Level
k: tRESTORE starts from the time VCC rises above VSWITCH.
STORE Cycle Inhibit and Automatic Power Up RECALL VCC 3.0 V VSWITCH
t STORE inhibit Power Up RECALL Software Mode Selection A13 - A0 (hex) 0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63
(24)
tRESTORE
E L
W H
Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL
I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
Power Active
Notes l, l, l, l, l, l, l, l, l, l, l, l, m m m m m m m m m m m m
ICC2 Active
L
H
The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C. m: While there are 15 addresses on the UL631H256, only the lower 14 are used to control software modes.
l:
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UL631H256
Symbol No. Software Controlled STORE/RECALL Cyclel, n 25 STORE/RECALL Initiation Time 26 Chip Enable to Output Inactive o 27 STORE Cycle Timep 28 RECALL Cycle Timeq 29 Address Setup to Chip Enable r 30 Chip Enable Pulse Width r, s 31 Chip Disable to Address Changer
n: o: p: q:
35
Min. Max.
45 Min. 45 600 10 20 600 10 20 0 30 0 Max. Unit ns ns ms ms ns ns ns
Alt. tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN
IEC tcR tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR
35
0 25 0
The software sequence is clocked with E controlled READs Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit). An automatic RECALL also takes place at power up, starting when VCC exceeds V SWITCH and takes tRESTORE. VCC must not drop below VSWITCH once it has been exceeded for the RECALL to function properly. r: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence. s: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR , than the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated.
Software Controlled STORE/RECALL Cyclet, u (E = HIGH after STORE initiation)
tcR (25)
tcR (25) ADDRESS 6
Ai E
ADDRESS 1 tw(E)SR tsu(A)SR (29)
(30)
th(A)SR
(31)
DQi
Output
td(E)S (27) td(E)R (28) VALID tdis(E)SR (26)
High Impedance
VALID
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
tcR (25)
Ai E
ADDRESS 1 tw(E)SR tsu(A)SR (29)
(30) (31) th(A)SR
ADDRESS 6 th(A)SR (31)
(29)
DQi
Output
High Impedance
tsu(A)SR
td(E)S (27) VALID tdis(E)SR (26)
td(E)R (28)
VALID
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the UL631H256 performs a STORE or RECALL. u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
t:
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UL631H256
Test Configuration for Functional Check
3V
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
VCC w
Input level according to the
relevant test measurement
VIH
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
VIL
ment of all 8 output pins
Simultaneous measure-
DQ0
1.1 k
VO 30 pF v 950
E W G
VSS
v: In measurement of tdis-times and ten-times the capacitance is 5 pF. w: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 F to avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions VCC VI f Ta = 3.0 V = VSS = 1 MHz = 25 C
Symbol CI CO
Min.
Max. 8 7
Unit pF pF
All pins not under test must be connected with ground by capacitors. Ordering Code Example Type Package S = SOP28 (330mil) Type 1 S2 = SOP28 (330mil) Type 2 Operating Temperature Range C = 0 to 70 C K = -40 to 85 C
x: on special request
UL631H256 S2
C
45 G1 Leadfree Option blank = Standard Package G1 = Leadfree Green Package x Access Time 35 = 35 ns (VCC = 3.0 ... 3.6 V) 45 = 45 ns (VCC = 2.7 ... 3.6 V)
Device Marking (example) Product specification
ZMD UL631H256S2C 45 Z 0425 G1
Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package
Internal Code
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UL631H256
Device Operation The UL631H256 has two separate modes of operation: SRAM mode and nonvolatile mode. The memory operates in SRAM mode as a standard fast static RAM. Data is transferred In nonvolatile mode from SRAM to EEPROM shadow (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. SRAM READ The UL631H256 performs a READ cycle whenever E and G are LOW while W is HIGH. The address specified on pins A0 - A14 determines which of the 32768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Noise Consideration The UL631H256 is a high speed memory and therefore must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal carefull routing of power, ground and signals will help prevent noise problems. Software Nonvolatile STORE The UL631H256 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the UL631H256 implements nonvolatile operation while remaining compatible with standard 32K x 8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a 1. 2. 3. 4. 5. 6. Read addresses Read addresses Read addresses Read addresses Read addresses Read addresses 0E38 31C7 03E0 3C1F 303F 0FC0 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Cycle program of the nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the STORE cycle the following READ sequence must be performed:
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be LOW for the sequence to be valid. After the t STORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. Software Nonvolatile RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read addresses Read addresses Read addresses Read addresses Read addresses Read addresses 0E38 31C7 03E0 3C1F 303F 0C63 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Automatic Power Up RECALL On power up, once VCC exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated. The voltage on the V CC pin must not drop below VSWITCH once it has risen above it in order for the RECALL to operate properly. Due to this automatic 10 April 7, 2005
UL631H256
RECALL,SRAM operation cannot commence until tRESTORE after VCC exceeds VSWITCH. If the UL631H256 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 k resistor should be connected between W and VCC. Hardware Protection The UL631H256 offers hardware protection against inadvertent STORE operation through VCC sense. For VCC < V SWITCH the software initiated STORE operation will be inhibited. Low Average Active Power The UL631H256 has been designed to draw significantly less power when E is LOW (chip enabled) but the cycle time is longer than 45 ns. When E is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the V CC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
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UL631H256
LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
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Zentrum Mikroelektronik Dresden AG Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: memory@zmd.de * http://www.zmd.de

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